Between them, the CoreLink CMN-600 coherent mesh network and DMC-620 dynamic memory controller are said to improve data throughput by a factor of five, halve memory latency and support SoCs with up to 128 ARMv8A cores.
Jeff Defillipi, senior product manager with ARM’s System IP group, said the development was in response to the increase in the number of connected devices. “VR is becoming more prevalent,” he offered, “and streaming VR requires a constant high bandwidth, which is extremely demanding.”
A further target for the new backplane IP is autonomous vehicles. “But we probably won’t see truly autonomous vehicles until we have car to car communications, enabling real time decisions,” he continued.
According to Defillipi, the latest additions to the backplane IP portfolio are based on a new architecture and will take products into the next decade. “The IP is built on the AMBA5 CHI; the highest performing AMBA bus,” he said.
Other new features include intelligent cache allocation. “This is software configurable,” Defillipi noted, “and can boost the performance of networks when passing packets. I/O devices can also decide whether they want to access cache or main memory.”
Although applicable in SoCs with up to 128 cores, Defillipi says 64 cores will be the ‘sweet spot’.