LONDON - Fabless FPGA vendor Achronix Semiconductor Corp.(Santa Clara, Calif.) has announced details of its Speedster22i HD and HPproduct families, claimed to be the first FPGAs to be built on a 22-nm manufacturingprocess technology.
The devices are the result of a foundry agreement with IntelCorp. announced in November 2010 and the first devices are due to sample in thethird quarter of 2012.
Both the HD (high density) and HP (high performance)families come loaded with a variety of high-speed data communicationsinterfaces hardwired. These include 10/40/100G Ethernet MACs, 100GbitInterlaken channels, PCI Express and DDR3 memory channels that run at up to2133 Mbps. In the case of the HD1000 device these are two, two, two and six respectively.
This optimizes the Speedster22i FPGAs for work in networkingand telecommunications equipment although the company stresses that the devicescan find applications in servers, high-performance computing, military,industrial and scientific applications. The large number of high speed memorychannels provides the industry's highest bandwidth FPGAs, Achronix claimed.
Achronix' existing product range is based on 65-nm processtechnology and the move to Intel's 22-nm FinFET process allows Speedster22ifamily to consume half the power at half the cost of high-end, 28-nm FPGAs.
"We worked closely with leading companies in thecommunications market segment to design our FPGAs to meet their performance,power, and cost requirements," said Robert Blake, Achronix's president andCEO, in a statement. "The combination of Intel's 22-nm process leadershipand our innovation in both the core fabric and embedded hard IP for targetedapplications means that our customers will have a high end FPGA solution that ishalf the power and half the cost of competing FPGAs," he added.
Achronix is starting its Speedster22i family with HD1000device which includes logic equivalent to about 1 million 4-input look up tableblocks, the fundamental blocks in many FPGA architectures. In fact there areonly 700,000 user-programmable LUTs as Achronix values its hard-wired IP asbeing equivalent to about 300,000 LUTs. The HD1000 also includes 84-Mbits ofembedded RAM. Eventually there will be four members of the synchronous HD range(see table) that will capable of being run at a maximum clock frequency ofabout 600 or 700-MHz, according to John Lofton Holt, chairman and founder ofAchronix.
The HP family is due to start sampling in the first quarterof 2013, Holt said.
The HP FPGAs use a self-timed architecture to allowoperation at up to 1.5 GHz clock frequency and are 3 to 4 faster thansynchronous FPGAs, the company said. The largest member of the HP family, theHP560, has 250,000 programmable LUTs and 64-Mbits of embedded RAM.
The use of the Intel 22-nm FinFET process technology bringsan advantage in terms of half the leakage power of 28-nm equivalents and 20percent less power consumption of custom logic implemented in the FPGA fabric.The result is up to 50 percent less total power consumption that 28-nm FPGAs,Achronix claimed.
Achronix did not give any indication of what it will chargefor HD or HP FPGAs. Engineering samples of the HD1000 will begin shipping in Q32012. The remaining HD and HP devices will be rolled out in the following 12months.
This story was originally posted by EETimes.