According to the team, while there are other methods that can achieve such fine lines, none of them are cost-effective for large-scale manufacturing.
Today's methods for producing features smaller than 22nm across generally require building up an image line by line, by scanning a beam of electrons or ions across the chip surface – a very slow process and therefore expensive to implement at large scale.
The new process integrates two existing methods. First, a pattern of lines is produced on the chip surface using standard lithographic techniques. That surface is chemically etched so that the areas that were illuminated dissolve, leaving the spaces between them as conductive wires that connect parts of the circuit.
Then, a layer of a block copolymer – a mix of two different polymer materials that naturally segregate themselves into patterns – is formed by spin coating a solution. The block copolymers are made up of chain-like molecules, each consisting of two different polymer materials connected end-to-end.
Finally, a top, protective polymer layer is deposited on top of the others using chemical vapor deposition. This top coat is said to constrain the way the block copolymers self-assemble, forcing them to form into vertical layers rather than horizontal ones.
The underlying lithographed pattern guides the positioning of these layers, but the natural tendencies of the copolymers cause their width to be much smaller than that of the base lines. Because the top polymer layer can additionally be patterned, the system can be used to build up any kind of complex patterning.