A data center (or datacenter) is a centralized repository for the storage, management, and dissemination of data and information. Many people tend to think of data centers in the context of search engines like Google and Bing; others regard data centers as being the purview of huge entities like Amazon; in reality, almost every organization of any significance has a data center facility that centralizes its IT operations and equipment and houses the network's most critical systems.
All data centers share the same priorities, although their weighting may vary depending on the target application. These priorities include power efficiency, scalability, flexibility, longevity, cost, and performance. Additional requirements include monitoring, security, and the ability to support new types of applications as and when they appear on the market.
Today's data centers are struggling to accommodate exponential growth in the amount of data being processed, searched, and disseminated. They are also faced with increasingly complicated software stacks necessary to satisfy the demands of services and security.
Modern CPUs are tremendously powerful and they are well-suited for high-level decision-making and control tasks, but they are not optimal for certain functions like unstructured search, the encryption and decryption of humongous amounts of data, machine learning, and packet processing. Furthermore, the computational power offered by CPUs cannot scale economically to keep pace with ever-increasing data center requirements.
The solution is hardware acceleration, which may be implemented using a variety of technologies, including ASICs, FPGAs, GPUs, and NPUs.
FPGAs are well known for their versatility, but many of them implement communications and control functions wholly, or in part, as soft IP. By comparison, Achronix's Speedster 22i FPGAs -- which are built on Intel�s advanced 22nm process technology -- implement all of their interface functions as hardened IP, thereby resulting in lower power consumption, reduced programmable logic fabric consumed (up to 400K fewer lookup tables required), faster clock rates in hardened IP versus soft implementations, and lower design complexity since the interface IP is already timing-closed.
(Source: Achronix)
In addition to selling Speedster 22i FPGAs as standalone devices, Achronix also supplies two Speedster22i-based boards: one aimed at development of networking and communication subsystems, providing 100 Gbps throughput plus the appropriate ports and memory capacity for these functions, and the second -- the Accelerator-6D -- targeted at high-performance computing (HPC) applications.
The Accelerator-6D PCIe form-factor accelerator board (Source: Achronix)
The folks at Achronix say that the PCIe form-factor Accelerator-6D accelerator board is the industry�s highest single-FPGA memory bandwidth, PCIe add-in card for high-speed data center acceleration applications.
The Accelerator-6D boasts a Speedster22i HD1000 FPGA (with 700,000 lookup tables) that connects to six independent memory controllers, thereby allowing for up to 192 GB of memory and 690 Gbps of total memory bandwidth.
Each DRAM controller on the HD1000 runs at 1,600 MT/s and connects to two SODIMMs allowing for single, dual- and quad-rank SODIMM and SORDIMM DDR3 operation. The board also has four QSFP+ connectors for 10G/40G Ethernet connectivity and supports PCIe Gen3 �8 operation.
The controllers for the DDR3, Ethernet, and PCIe interfaces are implemented as embedded hard blocks inside the HD1000 FPGA, which eliminates the requirement to use valuable programmable resources inside the FPGA to implement these functions. In addition, the embedded hard controllers guarantee timing on these complex high-performance interfaces, enabling designers to focus their valuable time on developing data center acceleration applications.
Accelerator-6D boards are available today at a 1-unit price of $7,500. The board comes with a power supply, one-year license for Achronix's ACE design tools, and multiple system-level reference designs for Ethernet, DDR3, and PCIe operation. Click Here for additional information.
Related posts:
- Madcap Ultrasound Engineers Send FPGA to 103,000 Feet
- Proceedings of the IEEE: Design Automation of Electronic Systems
- Programmable ASSP (pASSP) I/F Bridge for Mobile Image Sensors & Displays
- FPGA-Based Real-Time Spectrum Analyzer Sets New Record
- Stratix 10 MX: 1 TBps On-Chip Memory Bandwidth in Single FPGA
- New FPGA/SoC TFT LCD Display Controller IP Core
- Smart FPGA Debugging Tools Reduce Validation Times
— Max Maxfield, Editor of All Things Fun & Interesting 