PORTLAND, Ore -- Broadcom Corp Tuesday (April 24) announcedits fourth-generation Ethernet network processor, which it claims is theindustry's first chip to use massive parallelism by virtue of its 64packet-processing cores running at one gigahertz. Providing full-duplex 100Gbitper second performance, it can also be configured to provide a dozen 10-Gbitchannels.
"By 2015, there will be twice as many devices connectedto the Internet as there are people in the world, many of which will bestreaming video," said Dan Harding, senior director of marketing,infrastructure and networking at Broadcom. "As a result of this increasingdemand for bandwidth, the core of the network is going to need upgrading to100Gbit Ethernet over the next four years."
Broadcom claims that by the end of 2012, the number ofInternet-connected devices will exceed 7 billion. Over the next four years themajority of the content accessed from mobile devices will be high-bandwidthstreaming video, according to Broadcom. What's worse, application downloadswill balloon to 47 billion per year, according to the firm.
To meet this demand, Internet service providers are quicklyadopting 100-gigabit-per-second Ethernet, which is estimated to grow at a rateof 170% over the next five years, according to Infonetics Research Inc(Campbell, Calif).
Server Ethernet ports running at 100 gigabits per second will grow at a rate of 170% over the next four years. Source: Infonetics
Broadcom claims that it has addressed the need for morebandwidth with higher levels of integration which enabled it to reduce thepower and area of its fourth-generation network processor by 80%. And with itsmulti-threading support and specialized accelerators, its new network processortechnology can offload many tasks that previously required external FPGAs.
"The key technology that differentiates our 100 gigabitnetwork processor are our seven cores dedicated to necessary tasks such asalgorithmic look-up and packet generation," said Nicolas Tausanovitch,senior product line manager of infrastructure and networking. "By takingon tasks that previously had to be performed external FPGAs and expensive SRAM,designers using our chip can cut now the complexity and bill-of-materials costfor their line cards."
Using 40-nanometer design rules for its array of 64 packetprocessors, the BCM88030 also includes seven on-chip accelerators for commonfunctions including a programmable algorithmic look-up engine for massive IPv6tables using low cost DDR-3 DRAM, algorithmic access control list usingBroadcom's proprietary knowledge based processor, as well as a high-speedpacket parser and classifier.
This story was originally posted by EETimes.