Ian Lankshear, EnSilica’s CEO, noted: “Our partnership with Micrium to port µC/OS-III to eSi-RISC strengthens and broadens the eSi-RISC ecosystem significantly, opening a host of potential opportunities for our customers, while reducing time to market and the cost of embedded development.”
Jean Labrosse, Micrium’s president and CEO, added: “The combination pf µC/OS-III and eSi-RISC is already bearing fruit, with joint projects underway.”
The eSi-RISC family of configurable soft processor cores supports 16 and 32bit configurations and have been silicon proven in a variety of ASIC technologies down to 28nm.
Meanwhile, µC/OS-III is a pre-emptive and deterministic multitasking RTOS with optional round robin scheduling. The kernel’s memory footprint can be scaled to contain only the features required for the application and typically requires 6 to 24kbyte of code space and 1kbyte of data space.