Ron Moore, product manager in ARM’s physical design group, noted: “We’re seeing three things at 7nm from the designer’s perspective: process variation; routeability; and electrical properties.”
Process variation is becoming more of a challenge as feature size decreases, while smaller features are, in turn, affecting the ability to route a design. And electrical properties, including IR drop and electromigration, compound the problems.
“We’re working to put innovation into our IP to mitigate these challenges,” Moore contended, “while giving designers the same ‘look and feel’ as in previous generations.”
According to ARM, one of the challenges in developing the 7nm IP platform was to abstract some of the design complexities. In particular, the requirements of TSMC’s 7FF process were such that a new memory development methodology was required, with a memory compiler taking a cell based layout approach. This is said to bring more consistent patterns and a reduction in variation.
Moore noted that ‘porosity’ was being included in standard cells in order to improve local interconnect and routing in the first two metal layers. “That will leave more area for the SoC designer in the upper layers,” he added. “There is also porosity in M3 and M4 for pass through. When you have to change levels, that’s a problem and we want to reduce the number of times you need to change levels.”
ARM has also addressed the issue of powering the various areas of an SoC. “If you get the power grid wrong,” Moore said, “it will create congestion. We’ve built a Power Grid Architect that has knowledge about standard cells and resources. By asking a few questions, it allows designers to build an efficient power grid that’s correct by construction.
“Before, a designer might have spent three weeks to get a good optimised grid. We’ve encapsulated that knowledge to the point where a grid can be produced in minutes.”