“We started with this revolutionary concept — that instruction sets should be free and open – and were amazed by the incredible rippling effect this has had on the semiconductor industry because it provided a viable alternative to what was previously closed and proprietary,” said Krste Asanovic, SiFive’s chief architect. “The FE310 is a major step forward in the movement toward open-source and mass customisation and SiFive is excited to bring the opportunity for innovation back into the hands of system architects.”
The FE310 features SiFive’s E31 CPU Coreplex, a 32bit RV32IMAC core running at 320MHz. Additional features include a 16kbyte L1 instruction cache, a 16kbyte data SRAM scratchpad, hardware multiply/divide, debug module and an OTP non volatile memory. Peripherals include UARTs, QSPI, PWMs and timers. There are also multiple power domains and a low-power standby mode.
“SiFive has achieved a significant milestone for the RISC-V ecosystem,” said Rick O’Connor, executive director of the RISC-V Foundation. “We are thrilled to see the first commercial silicon based on RISC-V standards come to market and look forward to continued technology leadership from the SiFive team.”
Meanwhile, SiFive has contributed the FE310 RTL code to the open-source community, allowing chip designers to customise their own SoC on top of the base FE310.