DesignCon, coming Jan. 28-31 at the Santa Clara Convention Center, is positioned as the leading live event for chip and systems designers and software developers. It's got keynoted from top engineers at Cisco, NVidia, and National Instruments, as well as a wealth of tech training sessions.
In advance of the show, DesignCon is offereing a free pass to the show-floor exhibits.The free pass comes with an option to attend a dozen vendor-sponsored education and training classes.
If you're in interested in attending all the sessions, there are a variety of paid options, including an all-access pass.
Info Redux:Sessions: DesignCon Schedule Builder (shows all tracks).
DesignCon Registration (direct to registration page link):
Click here to register for DesignCon 2013, Jan. 28-31 at the Santa Clara Convention Center. Options range from an All-Access Pass to Free Expo Admission, which includes the option to attend a dozen tech training sessions.
And Don't Miss: DesignCon Free Education & Training
(Host: Agilent Technologies; Corporate Sponsore: Rambus; Diamond Sponsor: SiSoft; Diamond Sponsor: Teledyne LeCroy: Platinum Sponsor: Rohde & Schwarz)
Monday, January 28:• Challenges and Solutions in Characterizing a 10Gb Device (Agilent)
• PCI Express 3.0 Characterization,Compliance, and Debug for Signal Integrity Engineers (Teledyne LeCroy)
Tuesday, January 29:• Synchronous Time and Frequency Domain Measurements Using a Digital Oscilloscope (Rohde & Schwarz)
• Ensuring Validation & Analysis of Complex Serial Bus Link Models (Tektronix)
• USB 2.0 Compliance Testing (Rohde & Schwarz)
• Phase Noise and Jitter Measurements (Rohde & Schwarz)
• True Differential S-parameter Measurements / Rohde & Schwarz
• Synchronous Time and Frequency Domain Measurements Using a Digital Oscilloscope (Rohde & Schwarz)
• USB 2.0 Compliance Testing (Rohde & Schwarz)
• Phase Noise and Jitter Measurements (Rohde & Schwarz)
• True Differential S-parameter Measurements (Rohde & Schwarz)
• Ensuring Validation & Analysis of Complex Serial Bus Link Models (Tektronix)
• Advances in 3D SI Simulations of Interconnects for Chip/Package/PCB (CST of America Inc.)
Wednesday, January 30:• Making DDR4 Work For You (Agilent)
• Debugging to Find the Root Cause of Compliance, Limit or Mask Test Violations (Teledyne LeCroy)