The tools have attained the latest N6 and N5/N5P Design Rule Manual (DRM) and SPICE certification, advancing next-generation mobile application development. Cadence and TSMC are working with customers on N6 design starts both on production designs and test chips. Additionally, Cadence and TSMC have active N5/N5P customer engagements underway.
The certified tools support the Cadence Intelligent System Design strategy. Cadence’s integrated flow ensures that all the tools will work together seamlessly, and customers can download the corresponding N6 and N5/N5P process design kits (PDKs) to begin design projects now.
Cadence has delivered a fully integrated digital implementation and signoff tool flow, which has been certified on both TSMC’s N6 and N5/N5P process technologies. The Cadence full flow includes the Innovus Implementation System, Liberate Characterization, Liberate Variety Statistical Characterization, Quantus Extraction Solution, Tempus Timing Signoff Solution, Voltus IC Power Integrity Solution and Pegasus Verification System. Additionally, the Genus Synthesis Solution is enabled for these process technologies.
The digital and signoff tools provide EUV support across the flow, offering customers optimal power, performance and area (PPA). Some of the latest Cadence tool enhancements include expanded EUV layer support and back end of line (BEOL) layer modelling and middle end of line (MEOL) features.
The Cadence custom/analog tools certified on TSMC’s N6 and N5/N5P process technologies include the Spectre Accelerated Parallel Simulator (APS), Spectre X, Spectre eXtensive Partitioning Simulator (XPS), Spectre RF Option, Spectre Circuit Simulator, and Voltus-Fi Custom Power Integrity Solution, as well as the Virtuoso custom IC design platform, which consists of the Virtuoso Schematic Editor, Virtuoso Layout Suite and Virtuoso ADE Product Suite.
With the latest design methodologies and capabilities included with the Virtuoso Advanced Node Platform on TSMC’s advanced process technologies, customers will be able to achieve better custom physical design throughput versus traditional non-structured design methodologies via the advanced capabilities in the Virtuoso and Spectre tools.
Custom/analogue enhancements for TSMC’s advanced process technologies incorporate an accelerated custom placement and routing methodology, which enables customers to improve productivity and meet power, density and electro migration requirements.
Universal polygrid snapping and colour engine support features have been enabled in N6. Additionally, expanded design rule constraint support with area-based rule, asymmetric colouring rule, voltage-dependent rule (VDR) and analogue cell support, including guardring and dummy insertion are enabled for N5/N5P.
“Our ongoing collaboration with Cadence ensures that our customer’s requirements for design solutions and services are well-addressed and supported,” said Suk Lee, TSMC senior director, Design Infrastructure Management Division. “The joint efforts combining TSMC’s most advanced process technologies and our partners’ certified design tools can empower our customers to capture growth opportunities with faster time-to-market and successful silicon innovations for next-generation mobile application development.”
“We’ve broadened our collaboration with TSMC to include support for its advanced N5/N5P process technologies, enabling our customers to achieve optimal PPA results with our tools,” said Dr. Chin-Chi Teng, senior vice president and general manager of the Digital & Signoff Group at Cadence. “We’ve also achieved certification for N6 early design starts and are ready to support any customer transitioning from the N7 process technology who requires even more competitive advantages to deliver the most innovative, complex designs in a timely manner.”