The tools were certified for the Process Design Kit (PDK) and foundation library on the 7LPP process and confirmed to meet Samsung Foundry’s accuracy requirements, enabling systems and semiconductor companies to accelerate the delivery of 7LPP designs.
The RTL-to-GDSII design flow that has been certified for the 7LPP process technology is based on the Design Methodology (DM) of Samsung Foundry using an OpenRISC OR1200 design.
The Cadence digital and signoff tools are available via a quick-start kit and include the Innovus Implementation System, Genus Synthesis Solution, Joules RTL Power Solution, Conformal Equivalence Checking, Conformal Low Power, Modus DFT Software Solution, Voltus IC Power Integrity Solution, Tempus Timing Signoff Solution, Quantus Extraction Solution, Cadence Physical Verification System (PVS), Cadence CMP Predictor (CCP) and Cadence Litho Physical Analyzer (LPA).
“Our 7LPP process provides the best power, performance and area that we have seen so far in advanced FinFET nodes, and we expect this will provide great benefits for our customers’ next generation SoC designs,” said Ryan Sanghyun Lee, vice president of the Foundry Marketing at Samsung Electronics. “By working closely with Cadence, we have been able to ensure that our customers can get these benefits quickly and easily using the certified Cadence digital and signoff full flow.”
“Using our full RTL-to-GDSII reference flow, our customers can take advantage of the advanced-node innovation provided in the 7LPP process,” said KT Moore, vice president, product management in the Digital & Signoff Group at Cadence. “Our ongoing collaboration with Samsung Foundry enables us to provide the tools our customers require to quickly complete the most complex designs.”