The companies have also announced development progress on the third-generation 96-tier 3D NAND structure, providing a 50 percent increase in layers. These advancements in the cell structure continue the companies’ leadership in producing the world’s highest Gb/mm2 areal density.
Both NAND technology advancements use CMOS under the array (CuA) technology to reduce die sizes and deliver improved performance when compared to competitive approaches.
By leveraging four planes vs the competitors’ two planes, the new Intel and Micron NAND flash memory can write and read more cells in parallel, which delivers faster throughput and higher bandwidth at the system level.
The new 64-layer 4bits/cell NAND technology enables denser storage in a smaller space, bringing significant cost savings for read-intensive cloud workloads and is well-suited for consumer and client computing applications, providing cost-optimised storage solutions.
"With the introduction of 64-layer 4bits/cell NAND technology, we are achieving 33 percent higher array density compared to TLC, which enables us to produce the first commercially available 1 terabit die in the history of semiconductors," said Micron Executive Vice President, Technology Development, Scott DeBoer. "We’re continuing flash technology innovation with our 96-layer structure, condensing even more data into smaller spaces, unlocking the possibilities of workload capability and application construction."
“Commercialisation of 1Tb 4bits/cell is a big milestone in NVM history and is made possible by numerous innovations in technology and design that further extend the capability of our Floating Gate 3D NAND technology,” said RV Giridhar, Intel vice president, Non-Volatile Memory Technology Development. “The move to 4bits/cell enables compelling new operating points for density and cost in data centre and client storage.”