Geoff Lees, general manager of NXP’s microcontroller business, said the i.MX RT is intended for edge processing applications. “NXP sees this as relating to every connected device down to the MCU level. Everything will have some processing requirement, along with management, analytics, wireless connectivity and HMI support. And this device also has built in physical security.”
According to Lees, customers developing low cost applications have asked for a device which can support an RTOS running on a Cortex-A7 platform. “While we have done that,” Lees noted, “that carries a large overhead and the implementation is not as efficient as it could be.”
In the i.MX RT, the Cortex-A7 core is replaced by a Cortex-M7. “We use the M7 to increase real time performance,” Lees explained, “particularly latency. So we started with the i.MX6 UL, removed the A7 domain, along with the caches and so on, and dropped in an M7. The result is a device which is more optimised for real time applications. And we’ve gone from concept to production in less than 12 months.
“Running the M7 at high clock rates can bring power consumption penalties,” Lees continued, “but we are geared up to put the i.MX RT into production at 600MHz with 512kbyte of SRAM.”
At the moment, the part is targeted for production on an 40nm process and Lees claims the device will consume 100µA/MHz – up to three times less than comparable parts.
The first part in the range, the RT 1050, is sampling and will be in volume production shortly. “One thing we have focused on,” Lees continued, “is making sure real time response is in the nanosecond range – and the RT 1050 has a latency of about 20ns. We’ve also made sure that all SRAM on chip can be used either as tightly coupled memory or as general purpose RAM.”
As Lees noted, the RT 1050 resembles the i.MX6 UL. “We’ve retained the high performance communications features of the i.MX, but have added a number of peripherals to support MCU related tasks.” And he pointed out that, by removing the A7 core, enough die space was created to allow a DC/DC converter to be integrated on chip.
The BGA packaged device – which will sell for less than $3 – has been designed so that it can be used on a four layer PCB. “A typical i.MX needs six to eight layers,” Lees noted.
NXP will also be sampling a ‘cut down’ version of the chip at the end of 2017. The 1020 will come in a QFP with 256kbyte of SRAM, but Lees noted that some peripherals which don’t make sense for a QFP device will be omitted. “Wire bonding will also mean it has to run at 500MHz.”
More RT parts are in development. “While the 1050 comes with 512k of RAM, we’re working on parts with many times that,” Lees said, “as well as working on 28nm variants. Our target is 5Mbyte of RAM and that makes no sense on 40nm. Moving to 28nm will also halve the power consumption, so that’s significant.”
Further down the line, Lees expects MRAM to appear in the chips. “It’s good for economies of scale and it’s a back end process. Being able to take a standard design and overlay MRAM without impacting cost is very attractive. NXP recently presented a test chip with 8Mbit of MRAM,” he concluded. “It’s not near production, but watch this space.”
