As R&D progresses towards the 5nm technology node, the copper (Cu) wiring schemes in the chips’ BEOL are becoming more complex and compact. Shrinking the dimensions also reduces the wires cross-sectional area, driving up the resistance-capacitance (RC) of the interconnect systems and thus increasing signal delay.
“The emergence of RC delay issues started several technology nodes ago, and has become increasingly more challenging at each node. Through innovations in materials and process schemes, new BEOL architectures and system/technology co-optimisation, we can overcome this challenge as far as the 5nm node,” said Zsolt Tokei, director of the nano-interconnect programme.
To overcome the RC delay challenge, one viable option is to extend the Cu-based dual-damascene technology – the current process flow for interconnects – into the next technology nodes.
The solution features trenches created with critical dimensions of 12nm at 16nm. Metal-cuts perpendicular to the trenches are added to create electrically functional lines and then the trenches are filled with metal. Fully self-aligned vias were introduced to further area scaling.
Beyond 5nm, imec is exploring alternative metals that can potentially replace Cu as a conductor, including low resistive ruthenium. The company has realised Ru nanowires in scaled dimensions, with 58nm2 cross-sectional area, exhibiting a low resistivity, robust wafer-level reliability, and oxidation resistance – eliminating the need for a diffusion barrier.
