BERT to verify multiple high speed interface designs

  

“As of today, no other test and measurement company has a platform that tests all these new technologies at the same time,” said Alessandro Messina, EMEA wireline business marketing senior manager.

“The evolution to higher speed and to pulse amplitude modulation requires multiple testing channels, which means our test and measurement solutions must have multiple transmitters, interfaces and receiver interfaces to generate and receive signals and test the device.”

The new measurement platform MP1900A – and bit error rate tester – features 16 testing channels and eight slots.

Addressing the R&D market, the MP1900A is an all-in-one solution that measures high speed interface designs during the early development stage in electronic and optical devices, including optical transceivers used in servers and communications equipment, and optical transceivers/modules for M2M and IoT applications.

The built-in pulse pattern generator has an intrinsic jitter of 115fs rms, as well as typical Tr/Tf of 12ps. Total peak-to-peak jitter is 6ps max. and typical input sensitivity of the internal error detector is 15mV.

A link negotiation function is used to connect the SQA to the DUT for improved bus interface evaluation. Engineers can use the function to conduct PCI Express Gen 4 and Gen 5 tests, LTSSM status analysis, jitter generation, and CM/DM noise injection.

“Our platform has all that it takes to also test PCI Express for generations 1, 2, 3 and 4 and it is already ready for generation 5, which will come in one or two years from now,” Messina added.