The 96 layer stacking process, combined with advanced circuit and manufacturing process technology, sees a capacity increase of approximately 40% per unit chip size over devices featuring 64 layers. It also reduces the cost per bit and increases the manufacturability of memory capacity per silicon wafer.
According to Toshiba, the 96 layer part is likely to meet the performance demands of applications such as enterprise and consumer solid state disks, smartphones, tablets and memory cards.
In the near future, Toshiba says it will use its 96 layer process technology to create larger parts, including 512Gbit flash memories.
Devices featuring 96 layer BiCS FLASH technology will be made in Fab 5 at Yokkaichi Operations, as well as in the new Fab 2 and Fab 6, which is planned to open in summer 2018.
Meanwhile, Toshiba has announced that it has developed a BiCS FLASH memory capable of storing 4bit/cell. The prototype stores 768Gbit on 64 layers.
