SAN FRANCISCO -- Intel gave its first details public lookinto Ivy Bridge, the first processors to use its 22-nm tri-gate technology.Intel plans at least four major variants of the chip which packs 1.4 billiontransistors into 160-mm-square in its largest version.
Ivy Bridge packs 20 channels of PCI Express Gen 3interconnect and a Displayport controller, Intel's first chip to integratePCIe. The move marks one small step into the long term quest of what an Intelexecutive called terascale-class clients.
The first Ivy Bridge chip targets a range of desktop,notebook, embedded, and single-socket server systems with up to 8 Mbytes cache.Like previous Intel parts, it integrates a memory controller and graphics, nowupgraded to support DDR3L DRAMs and Microsoft DirectX 11.0 graphics APIs.
"We spent a lot of time on the modularity of this die tocreate different flavors of it very quickly," said Scott Siers, an Intelengineer who presented a paper on the chip at the International Solid-StateCircuits Conference here.
Specifically the largest die includes four x86 cores and alarge graphics block. It can be chopped along its x- and/or y-axis usingautomated generation tools to create versions with two cores or a smallergraphics block.
Siers said Ivy Bridge is Intel's first client chip tosupport low power 1.35V DDR3L and DDR power gating in standby mode. It handlesup to 1,600 MTransfers/s as well as 1.5V DDR3. A new write assist cache circuitprovides an average 100 millivolt power reduction.
The Displayport block supports three simultaneous displaysincluding one 1.6 GHz and two 2.7 GHz links with four lanes each.
The PCIe receiver uses a continuous time linear equalizerwith 32 gain control levels and a transmitter with a three-tap digital FIRfilter. The PCIe block also supports on die testing for jitter as well astiming and voltage margin measurements.
The chip's x86 and graphics cores can scale in data rates at100 and 50 MHz increments, respectively. Overall, the chip supports five powerplanes and 180 clock islands that can be separately gated.
In a separate ISSCC keynote, Dadi Perlmutter, chief productofficer for Intel, scoped out a long term vision of terahertz-class clients.Terahertz systems consume as much as three kilowatts today but could be reducedto 20W by the end of the decade using a broad variety of techniques, he said.
The techniques include optimizing chips to work at nearthreshold voltage levels, a subject of several Intel papers at ISSCC. Lowerpower internal and external interconnects are also needed, he said.
3-D IC packaging will be needed to lower power memory,Permutter said. Toward that end Intel is working with Micron and others on itsHypercube stacked memory design, he said. The design could boost memorybandwidth ten-fold while cutting power to eight pico-joules per bit, down from50-75 pj/bit in today's DDR3, he added.
In addition, "voltage regulation has to go into the ICitself because inductance is too big off chip or even on package," Perlmuttersaid. "When you have a lot of voltage regulators to turn on and off it becomesvery complex to do on a package, so we are working on getting power regulatorsinto the ICs," he said.
Perlmutter said he sees another 30 years of engineeringneeded in computing. "For people who thought they could retire from thisindustry, I say there's a lot more to do," he said.
This story was originally posted by EETimes. 
