MANHASSET, NY -- Cadence Design Systems claims thatNetronome designers achieved a 29% reduction in power consumption usingCadence's latest Encounter 11.1 technology thereby providing performanceadvantage on its low-power "green" SoCs targeting the secure virtualcloud and data center markets.
According to Netronome, its OEM customers have tremendousconstraints on power budgets, which required the company to optimize itshigh-performance 40 Gbps NFPs (network flow processor) for low-powerconsumption for use in their customers' switches, routers, load balancing, andcyber-security platforms.
"Using the complete Cadence Encounter RTL-to-GDSIIflow, we were able to tape out a complex 1.4-GHz 40-core micro-engine-basednetwork flow processor on schedule, achieving a 29% power savings and 10% improvementin timing," said Jim Finnegan, senior vice president, Silicon Engineeringat Netronome, in a statement.
Netronome engineers were particularly impressed with thenewly integrated Clock Concurrent Optimization (CCOpt) technology in theEncounter flow and its unique ability to optimize clocks and data-pathsimultaneously, thus eliminating several manual design steps and achievingsuperior performance, power, and area results on their design.
Netronome engineers were tasked with improving chip powerefficiencies across multi-mode, multi-corner, and on-chip variation scenarios.Implementing robust clock trees that consume less dynamic switching and staticleakage power without compromising on performance was difficult under suchextreme requirements.
Furthermore, as chip power consumption increases, it costsmore to design, fabricate, operate and cool devices and systems. Clocks are thebackbone of all digital chips, and a fundamentally different approach to clockconstruction and optimization was needed.
According to Cadence, traditional clock tree synthesis (CTS)tools and methodologies are insufficient for advanced node, high-performancedesigns due to the growing gap between pre- and post-CTS design timing. CCOpttechnology bridges the gap by re-focusing CTS directly on timing -- not skewminimization -- and combining this timing-driven CTS with concurrentlogic/physical optimization.
This story as originally posted by EETimes.
