PORTLAND, Ore -- Reaching the advanced semiconductor processnodes at 22-nanometer and beyond requires accurate three-dimensional (3-D)models of the proposed physical structures to obviate the need for repeatedtrial-and-error design cycles. In fact, the International Technology Roadmapfor Semiconductors has designated modeling 3D physical structures as a"grand challenge" at advanced processing nodes.
One of the few tools capable of modeling the ultra-compactstructures of FinFETs and other 3-D transistor structures is SEMulator3D, whichwas originally created by EDA software house Conventor Inc (Cary, NorthCarolina) for MEMS designs, but which today is used almost exclusively foradvanced semiconductor designs. IBM, for instance, has chosen SEMulator3D todesign its FinFETs at the 22-nanometer node and beyond.
"SEMulator3D has helped IBM predict problems thatotherwise would only have been found by subsequent testing and physical failureanalysis," said David Fried, 22-nm chief technologist at IBM.
The latest iteration of SEMulator3D 2012 now supports 64-bitvoxels (3-D pixels that can be filled with any semiconductor material) enablingultra-accurate modeling of 3-D semiconductor structures at advanced processingnodes.
SEMulator3D can model the micro-electro-mechanical structures on the most advanced semiconductors such as this FinFET SRAM cells with a high-K metal gate.
"Voxels are 3-D versions of pixels -- the sum total ofall your voxels is your physical design," said Ken Greiner, architect andmanager of SEMulator3D. "And now that they have 64-bit precision, it ispossible to achieve extremely fine details for designs beyond the 28-nmnode."
SEMulator 2012 also has fully automated the setting ofboundary conditions for all process steps, thereby removing a previous barrierto accurate simulations of advanced node designs that are strongly affected bythe rough edges that result from using 193-nm light to illuminate the 22-, 14-,and 10-nm masks being designed today.
Besides front-end designs, SEMulator3D is also finding usesin design-rule "brain storming," failure analysis and metrology forboth semiconductors and MEMS, according to Coventor.
This story was originally posted by EETimes.
