SAN FRANCISCO—Mentor Graphics Corp Wednesday (Feb. 22) announced the expansion of support for UVM (Universal Verification Methodology), a standardized methodology for IC design verification.
Mentor (Wilsonville, OR) introduced UVM Express, described as a way to progressively adopt a UVM methodology for teams that have not yet done so.
For other verification teams that have already established a UVM-based verification environment, but are challenged to move their trusted verification approach up in abstraction where a new level of system verification can be achieved, Mentor introduced UVM Connect, which provides standard TLM 1.0 and TLM 2.0 connectivity between models written in SystemC and UVM SystemVerilog, according to the company.
This story as originally posted by EE Times.
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