Interested in high-speed, high quality communications at the chip, board and system level? If so here are ten reasons to come to Santa Clara at the end of January 2013.
DesignCon is an exhibition and conference that addresses electronics from the chip and packaging level on up. It addresses issues around components, connectors and cabling at the board- and systems level and brings together EDA, test, measurement and things related to multi-GHz performance.
Check out the list below for a preview and come to the event, which runs from Monday, Jan. 28 to Thursday Jan. 31. The expo with, more than 130 exhibitors scheduled to attend, takes place on the middle two days, Jan. 29 and 30. The event is organized by UBM Tech, the publisher of
EE Times.
1) Content crafted by engineers, for engineersIt is the presence of relevant, well-presented, must-learn information that justifies traveling to any conference and exhibition. And the program for DesignCon is crafted by engineers, for engineers.
The technical program committee is comprised of senior and distinguished engineers and deep-dive specialists from both large and small companies. They have helped select quality presentations from their peers. Too many to list here, their affiliations cover the range from Agilent to Xilinx. If you are interested in seeing exactly who has been involved devising this year's program go to:
http://designcon.com/santaclara/conference/technical-program-committee.php2) Make yourself better with training, education Ever heard of speed training? It's like speed dating but without the disappointment and you get to learn a lot of interesting stuff. And there are a few examples of speed training due to be staged in the Chiphead Theater on the expo floor during the event.
Eric Bogatin, signal integrity evangelist with Bogatin Enterprises, is hosting
A pot pourri of SI puzzlers on Tuesday (Jan. 29) at 1:00pm. In 40 minutes he will look at five signal integrity issues and lead a debate on possible solutions. For extra credit, bring your own puzzles to share.
In addition, Agilent Technologies Inc., one of the sponsors of DesignCon 2013, is offering two free educational workshops. The first is scheduled to take place on Monday Jan. 28 at 1:30pm and over three hours covers the
measurement of jitter at 10-Gbps. The second workshop, entitled
Making DDR4 work for you takes place on Wednesday Jan. 30 starts at 8:30am.
Conference content selected by engineers for their peers is a key part of DesignCon 3) To be or not to be In another speed-training event engineers and managers from Synopsys have decided to put on a dramatic presentation. The plot revolves around a young signal integrity engineer trying to get through his first gigabit design review.
Dramatis Personae
Wi Can: a young signal integrity engineer
Prof. von Brawny: a technical guru
Mr. Nosebettur: senior signal integrity engineer
Mr. Sellzit: marketing manager
Mr. Gitterdun: engineering manager
This takes place on Wednesday (Jan. 30) at 2:00pm.
Next: A mix of youth, teardowns and supply chain matters
