SANTA CLARA, Calif.–Memory chip vendor Micron Technology Inc. plans to place NAND flash along with DRAM on memory modules that ride the DDR4 bus when arrives in about 18 months. The company believes Microsoft Windows will support the so-called Hybrid DIMMs that could pack more than 256 Gbytes of memory.
The move gives flash a new position in the computer memory hierarchy, ahead of today’s solid state drives that ride the PCI Express bus. The Hybrid DIMMs will be more expensive than SSDs but likely offer greater performance with memory access times measured in nano- rather than microseconds.
Both OEMs and end users have been approaching Micron with applications for hybrid DIMMs including in-memory databases and more. Micron (Boise, Idaho) believes the modules will be used as faster SSDs with large DRAM caches, DRAM modules with flash as swap space or as flash block storage assisted by DRAM.
The hybrid DIMMs use a special controller as the main interface to the processor. They also have a separate flash controller.
Support under Windows is a key enabler for hybrid DIMMs. So far Microsoft has not made any public comments on its plans, but over the last six months it has held and asked for multiple meetings with Micron on the technology.
“My read is they are signed up, they keep asking for more meetings,” said Ryan Baxter, a senior manager of business development for Micron who presented at the
Linley Data Center Conference here.
Micron is doing its own work enabling hybrid DIMMs under Linux. It expects to roll out that software in time for the DDR4 products.
Samsung is rumored to have expressed interest in the technology as well. Neither Samsung nor Microsoft responded to inquiries at press time.
Separately, Micron and partner Gigatech Products are already sampling so-called non-volatile DIMMs. They use flash and an ultracapacitor to back up DRAM in the event of a power failure. Netlist Inc. (Irvine, Calif.) is said to ship similar products.
Long term, Micron plans to have versions of its Hybrid Memory Cube (HMC), a 3-D memory and logic stack, suitable for integration in partner ASICs and FPGAs. “They will get access to interface technology…the SoC guys are interested,” said Baxter.
The current HMC design uses an interface with 16 serdes each running at 10 Gbit/s, tunable to 15 Gbits/s. The device will have a 300 GByte/s bandwidth in a version coming about 2016.
Click on image to enlarge.The slide above shows the concept of a hybrid DIMM. In the following pages, Micron foils show its ideas for a next-generation version with a DRAM replacement, the gap these products fill in the memory hierarchy and the non-volatile DIMMs Micron is sampling today.
