The16-gigabyte (GB) HBM2E is intended to maximize high performance computing (HPC) systems and help system manufacturers to advance their supercomputers, AI-driven data analytics and state-of-the-art graphics systems.
The 16GB capacity is achieved by vertically stacking eight layers of 10nm-class (1y) 16-gigabit (Gb) DRAM dies on top of a buffer chip. This HBM2E package is then interconnected in a precise arrangement of more than 40,000 ‘through silicon via’ (TSV) microbumps, with each 16Gb die containing over 5,600 of these microscopic holes.
According to Samsung, the device is able to provide a highly reliable data transfer speed of 3.2 gigabits per second (Gbps) by leveraging a proprietary optimised circuit design for signal transmission, while offering a memory bandwidth of 410GB/s per stack. The HBM2E can also attain a transfer speed of 4.2Gbps, the maximum tested data rate to date, enabling up to a 538GB/s bandwidth per stack in certain future applications. This would represent a 1.75x enhancement over Aquabolt’s 307GB/s.
Samsung expects to begin volume production during the first half of this year.
