The memory cell, dubbed “Twin BiCS FLASH”, uses semi-circular Floating Gate (FG) cells and achieves program slope and a larger program/erase window at a much smaller cell size compared to conventional circular Charge Trap (CT) cells.
The company says these attributes make this new cell design a promising candidate to surpass four bits per cell (QLC) for significantly higher memory density and fewer stacking layers.
KIOXIA explains that the circular control gate provides a larger program window with relaxed saturation problems when compared with a planar gate because of the curvature effect, where carrier injection through the tunnel dielectric is enhanced while electron leakage to the block (BLK) dielectric is lowered. In this split-gate cell design, the circular control gate is symmetrically divided into two semicircular gates to take advantage of improved program/erase dynamics.
The conductive storage layer shown in the above image is employed for high charge trapping efficiency in conjunction with the high-k BLK dielectrics, achieving high coupling ratio to gain program window as well as reduced electron leakage from the FG. This relieves the saturation issue.
Going forward, KIOXIA says its research and development efforts will focus on innovation in flash memory, including continuing Twin BiCS FLASH development and seeking its practical applications.
