Lattice introduces CrossLinkPlus FPGA family

  

CrossLinkPlus devices are low power FPGAs which feature integrated flash memory, a hardened MIPI D-PHY and high-speed I/Os for instant-on panel display performance, and flexible on-device programming capabilities.

Lattice also provides ready-to-use IPs and reference designs to speed up the implementation of enhanced sensor and display bridging, aggregation, and splitting functionality, a common requirement for industrial, automotive, computing, and consumer applications.

For developers looking to add multiple image sensors and/or displays to embedded vision systems, CrossLinkPlus FPGAs offer a small (3.5 x 3.5 mm), low power (< 300 µW) device that has been specifically optimised for embedded vision applications with features like a hardened MIPI D-PHY, broad high-speed I/O support for interfaces like OpenLDI and RGB, and on-chip non-volatile flash memory.

CrossLinkPlus uses on-chip flash to support instant-on and flexible device reprogramming in the field.

“The use of MIPI D-PHY in applications ranging from industrial control equipment displays to AI security cameras is booming as OEMs look to capitalise on the economies of scale driven by the MIPI ecosystem,” said Peiju Chiang, product marketing manager, Lattice Semiconductor. “Lattice’s new CrossLinkPlus FPGAs combine flexible programmability and speedy parallel processing associated with FPGAs with vision-specific hardware, software, pre-verified IPs and reference designs. This lets OEMs devote more time to building applications and less time enabling standard functions that don’t offer any competitive differentiation.”

Key features of the CrossLinkPlus family of FPGAs include:

  • On-device reprogrammable flash memory to enable instant-on (< 10 ms)
  • Hardened, pre-verified MIPI D-PHY interface supporting speeds up to 6 Gbps per port
  • Broad support for high-speed I/O interfaces such as LVDS, SLVS and subLVDS
  • Comprehensive IP library, including MIPI CSI-2, MIPI DSI, OpenLDI transmitters and receivers. These IPs are compatible with other Lattice FPGAs for easy design portability.
  • Fully compatible with the Lattice Diamond® design software tool flow, from synthesis and design capture through implementation, verification, and programming
  • Power consumption as low as 300 µW (standby) or 5 mW (operating)