Using this test vehicle, imec has obtained a 30 percent improvement in resistance-capacitance product (RC) compared to previous generations, without impacting on reliability. The need for implementing scaling boosters such as self-aligned vias and self-aligned blocks in 3nm and beyond interconnect technologies has been demonstrated.
While the dimensional scaling of traditional front-end technologies is expected to slow down, the back-end-of-line dimensions will need to keep on scaling with ~0.7X to keep up with the required area scaling. For the 3nm logic technology node, M2 interconnect layers with metal pitches as tight as 21nm will need to be manufactured while preserving the back-end-of-line’s performance. This implies a tight control of the RC delay, while maintaining good reliability.
The test vehicle also performs well in terms of reliability: no electromigration failures were observed after 530 hours at 330°C, and dielectric breakdown (TDDB) measurements demonstrated a time-to-failure>10 years at 100°C.
To pattern the M2 layer, a hybrid lithography approach was proposed, using 193nm immersion-based self-aligned quadrupole patterning (SAQP) for printing the lines and trenches, and extreme ultraviolet lithography (EUVL) for printing the block and via structures. The test vehicle implemented a barrier-less ruthenium (Ru) metallization scheme and an insulator with dielectric constant k = 3.0.
First results also demonstrate that the proposed interconnect technology can be improved by adding scaling boosters, including buried power rail, SuperVia, self-aligned blocks, fully self-aligned vias and double self-aligned blocks.
Image: Measured resistance per link for 100 via chains with 21nm metal pitch shows excellent agreement with simulation (left) and elemental mapping of Ru lines and vias (right)
