VIP for DisplayPort 2.0 is intended to enable designers to complete the functional verification of their mobile, Audio-Visual and AR/VR system-on-chip (SoC) designs with less effort and greater assurance that the design will operate as expected.
The latest VIP for DisplayPort 2.0 has been architected to meet the specifications of the new standard - enhancing design verification productivity, ensuring high-quality designs and delivering maximum performance. It offers the industry’s most comprehensive protocol validation solution for DisplayPort designs and includes a configurable bus functional model (BFM), a protocol monitor and a library of integrated protocol checks to optimise verification predictability. In addition, the VIP has been designed for easy integration into testbenches at IP, SoC and system levels, helping engineers reduce time to first test and accelerate verification closure.
“By releasing the first-to-market VIP for DisplayPort 2.0, we’re enabling early adopters to ensure their designs comply with the specification while achieving the fastest path to IP verification closure,” said Paul Cunningham, corporate vice president and general manager of the System & Verification Group at Cadence. “We have been working closely with early adopters of the spec, which has enabled us to provide a solid and high-quality verification IP for advanced designs for automotive, mobile and machine learning applications.”
The Cadence Verification IP portfolio, including the latest VIP for DisplayPort 2.0, is part of the broader Cadence Verification Suite and is optimised for Xcelium Parallel Logic Simulation, along with supported third-party simulators.
The Verification Suite is comprised of best-in-class core engines, verification fabric technologies and solutions that increase design quality and throughput, fulfilling verification requirements for a wide variety of applications and vertical segments.
