The Speedster7t family is described as going beyond traditional FPGA solutions offering ASIC-like performance, FPGA adaptability and enhanced functionality to streamline design.
The device has been optimised for high-bandwidth workloads and features a new 2D network-on-chip (NoC), and a high density array of new machine learning processors (MLPs) blocks, which have been optimised for high-bandwidth and AI/ML workloads. Blending FPGA programmability with ASIC routing structures and compute engines, the company is describing the Speedster7t family as a new “FPGA+” class of technology.
“The growth potential for AI/ML is astounding, and the use cases are rapidly evolving, and we are offering a new solution to address the varying requirements of high performance, flexibility and time to market with our new FPGA+ class of technology,” said Robert Blake, president and CEO of Achronix.
The Speedster7t saw Achronix’s engineering team rethink the entire FPGA architecture to balance on-chip processing, interconnect and external I/O, to maximise the throughput of data-intensive workloads such as those found in edge- and server-based AI/ML applications, networking and storage.
The Speedster7t devices are designed to accept massive amounts of data from multiple high-speed sources, distribute that data to programmable on-chip algorithmic and processing units, and then deliver those results with the lowest possible latency. They include high-bandwidth GDDR6 interfaces, 400G Ethernet ports, and PCI Express Gen5 — all interconnected to deliver ASIC-level bandwidth while retaining the full programmability of FPGA.
The device has been manufactured on TSMC’s 7nm FinFET process and the first devices and development boards for evaluation will be available in Q4 2019.
