Aldec is a specialist in mixed HDL language simulation and hardware-assisted verification for FPGA and ASIC designs.
The latest release of HES Proto-AXI, Release 2018.12, features new HES board HES-XCVU9P-ZU7EV support including a comprehensive collection of FPGA prototyping resources, such as Vivado board definitions and sample designs.
The other important component of the package, the HES Proto-AXI module, now includes interrupt support and a Python API.
Board packages facilitate the development of an FPGA-based prototype and its operating environment. Board definition files enable the quick connection of the design to on-board peripherals in the Xilinx Vivado design environment. Sample projects contain complete source codes and can be used as starting points for the user’s applications, greatly improving both productivity and shortening the total time of the overall prototyping stage.
The new HES Proto-AXI also provides a unique host interface with AMBA AXI4 interconnect that can be used to bridge the prototyped design to either a PC host (via PCIe interface) or a Xilinx Zynq/ARM Cortex embedded host.
Interrupts support is a new feature of HES Proto-AXI 2018.12 and allows for the replacement of register pooling with asynchronous interrupt events from hardware to software, enabling more robust test applications. The addition of a Python wrapper to HES Proto-AXI API further empowers rapid software development.
With software support and a ready-to-use HES Proto-AXI Host Interface, Aldec HES boards can also be used as hardware accelerators for algorithms in HPC as well as High Frequency Trading (HFT) applications.
The new HES Proto-AXI 2018.12 software is available now.
