ATE-Connect test technology set to dramatically speed up silicon debug and bring-up

  

The ATE-Connect technology creates an industry-standard interface to eliminate communication barriers between proprietary, tester-specific software and design-for-test (DFT) platforms. The technology accelerates debug of IJTAG devices, helps speed up product ramps, and reduces time-to-market for products in 5G wireless communications, autonomous driving, and artificial intelligence.

Mentor has also announced that Teradyne’s UltraFLEX test solution fully supports the interface through its PortBridge technology.

Despite broad industry adoption of the IJTAG (IEEE 1687) test architecture for chip-level testing, many companies maintain very different approaches for converting chip-level test patterns into tester formats, as well as for debugging tests on automatic test equipment (ATE). Consequently each specific chip must have test patterns written by DFT engineers, and then translated by test engineers to debug each scenario on each tester type. Test engineers typically work at a low, detailed level with clock cycles, while DFT engineers work at a higher level using IJTAG.

The differences in tools and techniques between the two can lead to confusion on how to most efficiently debug chips, resulting in long delays in the IC product lifecycle.

Using the TCP/IP network protocol, the Mentor ATE-Connect technology provides IJTAG commands to the device under test and receives data from the device on the ATE – all while keeping the sensitive design information in the realm of the Tessent SiliconInsight tool and only providing the required stimulus to the device under test on the ATE. With this standard network communication, customers can leverage their existing secure networks to enable seamless interaction with testers around the globe.

Commenting Brady Benware, senior marketing director for the Tessent product family at Mentor, said. “Directly linking the power of IJTAG with the ATE has eliminated a significant bottleneck in their debug and characterization processes. With this solution, customers may be able to achieve silicon bring-up in days instead of weeks.”