Cadence digital and signoff tools optimised for TSMC’s 5nm and 7nm+ process are designed to provide EUV support at key layers and associated design rules that enable customers to achieve power, performance and area (PPA) savings at these advanced nodes. Some of the enhancements for the 5nm and 7nm+ process include via pillar-aware synthesis and feed forward guidance with the Genus Synthesis Solution, as well as a pin-access control routing method for cell electromigration (EM) handling and statistical EM budgeting support.
In addition to the tools certified for TSMC’s 5nm and 7nm+ process technologies, the Liberate Characterization portfolio and the Liberate Variety Statistical Characterization Solution have been validated to deliver accurate Liberty libraries, including advanced timing, noise and power models. The solutions utilised innovative methods to characterise Liberty Variation Format (LVF) models, according to Cadence. This enables accurate process variation signoff for low-voltage applications and the ability to create EM models enabling signal EM optimisations and signoff.
“Our 5nm process has matured to a great degree with customers doing early design starts, while our 7nm+ technology is production ready and actively in use with mutual customers,” said Suk Lee, TSMC senior director, Design Infrastructure Marketing Division.
“We’ve continued our close collaboration with TSMC on advancing 5nm and 7nm+ FinFET adoption by providing customers with access to the latest technical capabilities for advanced-node design creation,” said Dr. Chin-Chi Teng, senior vice president and general manager of the Digital & Signoff Group at Cadence. “Based on aggressive new R&D optimisations and performance improvements to our digital and signoff and custom/analogue tools, customers can deliver innovative, reliable end products in their respective markets within tight timelines.”
