A couple of weeks ago the folks from Blue Pearl announced that the latest generation of their EDA tools boast a plethora of SystemVerilog and FPGA enhancements (
Click Here to see that announcement).
Well, I just heard that they are offering free hands-on workshops at their facility in Santa Clara, California. Currently there are three dates: February 21, March 15, and April 19, but I wouldn’t be surprised if more were offered later.
The official notification was as follows:
Hello Designers, we are excited to announce Release 6.0 of Blue Pearl Software Suite which includes comprehensive RTL analysis, clock-domain crossing (CDC) checks, and automatic SDC generation for SoC designs. Blue Pearl Software Suite is easy to use for any level of ASIC/FPGA designers.
Our Software Suite which runs on Windows and Linux, offers multi- language (Verilog, SystemVerilog and VHDL) support, and supports major synthesis flows. Designers can mix and match hardware languages in the same design with language checking that matches downstream tools. Its visualization and validation technology gives immediate feedback for validating its automatically generated timing constraints.
We would like to invite you to our SoC Design Workshop. At our Workshop, we will share information about how our tools specifically address the needs of designers and improve productivity and design quality.
Wondering why you need to attend this workshop? We understand the challenges of designing SOCs that run at >150MHz, with more than 10 clocks. You should attend this workshop if you are interested in learning about at least one of the following:
- How to reduce your design iterations and close timing faster
- How to improve performance of your designs
- How to apply advanced techniques to close timing
- How to reduce the pain points in today’s methodologies using the latest innovations in EDA
- How to address these hard to find clock domain crossing issues
- How to clean your RTL code
Click Here to register and join us at our Workshop.
Click Here to learn more about the Blue Pearl Software Suite. .
Join us at DV Con Expo (Feb 28-29) to participate in a draw for an Apple TV.
If you found this article to be of interest, visit
Programmable Logic Designline where you will find the latest and greatest design, technology, product, and news articles with regard to programmable logic devices of every flavor and size (FPGAs, CPLDs, CSSPs, PSoCs...).
Also, you can obtain a highlights update delivered directly to your inbox by signing up for my weekly newsletter – just
Click Here to request this newsletter using the Manage Newsletters tab (if you aren't already a member you'll be asked to register, but it's free and painless so don't let that stop you [grin]).
