LONDON – Processor IP licensor ARM Holdings plc (Cambridge, England) has said it continues to work with all the major EDA companies after
EE Times asked about claimed improvements in performance and power consumption trade-offs claimed for the design of system-chips (SoCs) based on Cortex A-series processor cores made using design tools from Cadence Design Systems Inc. (see
ARM, Cadence tune support for processor design).
In an emailed response John Heinlein, vice president of marketing at ARM's physical IP division, said: "The fundamentals of the POP [processor optimization package] IP platform are independent of EDA tools. With this announcement, for both Synopsys and Cadence tool users we now have scripts and recommendations available so that the user of either tools can achieve a result that is far more optimized and at superior time-to-market than without POP IP.
Heinlein added that the Cadence version of POP IP flow had been greatly improved in usability and pre-verification but did not comment on its performance relative to similar POP IP flow with Synopsys.
"In practice, in most cases SoC designers use a blended flow of several different EDA vendors. It is somewhat rare to see a company using tools from just one vendor top to bottom. The POP technology now fully supports Cadence and Synopsys tool flows and also blended flows. We also focus on the best point solution tools in specialty areas, such as Mentor for test and repair as well as other specialty providers in other areas," said Heinlein in the email.
"Our customers use a range of EDA tool solutions, and one of the benefits of ARM physical IP products is we support customer choice in tool adoption including support for hybrid flows," Heinlein concluded.
Related links and articles:
ARM, Cadence tune support for processor design
Microelectronics Olympiad backed by Synopsys, IEEE
EE Times' 20 hot technologies for 2012
Silicon 60 v13.0
