Cadence says it has prototyped its first IP interface in silicon for a preliminary version of the DDR5 standard being developed in JEDEC.
The Cadence test chip was fabricated in TSMC’s 7nm process and is said to achieve a 4400 megatransfers per second (MT/sec) data rate, which is 37.5% quicker than the fastest commercial DDR4 memory at 3200MT/sec.
With this key milestone, Cadence says SoC providers developing high-speed memory subsystems for high-end server, storage and enterprise applications, can start developing their DDR5 memory subsystems with silicon-tested PHY and controller IP from Cadence.
“As part of Cadence’s DDR PHY validation and interoperability program, Micron has provided Cadence with engineering prototypes of the first memory for a preliminary version of the DDR5 standard,” says Ryan Baxter, director of Data Center segment, Compute and Networking Business Unit, at Micron.
Cadence also revealed that its full suite of digital, signoff and custom/analog IC design tools, along with advanced IC packaging design solutions, support the new TSMC WoW stacking technology.
Cadence says it provides flows, tools and methodologies that enable TSMC customers to manage the top-level connectivity and verification of their chip integration solutions as part of the overall design process.
The tools have been optimised to provide a complete integrated flow for implementing WoW chip integration techniques within the existing toolchain. These include – but are not limited to – the Innovus Implementation System; the QuantusExtraction Solution; and the Voltus IC Power Integrity Solution. More information on this can be found, here.
