The enhancements affect almost every Virtuoso product, and the updated Virtuoso System Design Platform now allows system engineers to edit and analyse the most complex heterogeneous systems.
It enables package, photonics, IC analogue and RF engineers to work through a single platform and use the full breadth of the platform’s design applications. At its heart is a set of technologies that enable simultaneous edits across multiple process design kits and technologies. The platform also provides interoperability with Cadence SiP Layout and the Sigrity analysis technology portfolio providing users with a comprehensive chip-to-board toolset.
This new release has seen Cadence incorporate innovative advanced-node methodologies that speed the designs done in process technologies from 22nm down to 5nm.
By collaborating with foundries, ecosystem partners and customers, Cadence has developed advanced technologies that automatically manage process complexities allowing engineers to focus on their designs. For example, in circuit design and analysis, advanced statistical algorithms specifically targeting FinFET designs uncover circuit variances earlier, reducing design variation analysis time by approximately 20%.
In layout design, a unique multi-grid system abstracts complex design rules of the latest 7nm and 5nm processes, while allowing engineers to increase their use of placement and routing technologies to significantly increase layout design productivity. Using these techniques with the enhancements made to the advanced methodology reduces layout effort by >3X in 7nm production designs.
Cadence has also made several enhancements to improve analogue design and analysis. The Virtuoso Analog Design Environment (ADE) simulation throughput is improved by up to 3x due to enhanced integration with the Cadence Spectre Circuit Simulator, increasing simulation throughput and using advanced analysis to reduce design iterations.
Capabilities were added to the Virtuoso ADE Verifier to centralise cross-domain electrical specifications so the path to standards compliance (e.g., ISO 26262) is streamlined by approximately 30 percent.
The Virtuoso Layout environment is also evolving from an electrically aware layout to the industry’s first electrically and simulation-driven layout using sets of in-design technologies to ensure circuit integrity and performance.
This new simulation-driven layout addresses many of the electromigration (EM) and parasitic challenges of critical circuits and advanced-node designs. To increase layout automation, the new environment has introduced breakthrough techniques for hierarchical floorplanning and planning along with new placement and routing automation technologies to increase layout design productivity and throughput and to shorten layout turnaround time.
According to Cadence, one of the big challenges facing designers is dividing layout tasks among the design team. The Virtuoso platform now features a concurrent real-time team design editing capability, allowing teams to distribute layout tasks and perform what-if explorations - seen as particularly useful for design-rule check (DRC) fixing, chip finishing and manual routing.
Cadence believes that this new layout environment with electrically driven routing and wire editing, real-time design editing and design planning techniques will help to improve productivity by up to 50 percent.
