The folks at
Tabula have confirmed previous speculation that they are implementing a family of 3PLD products (what the rest of us would call 3D FPGAs –
Click Here to see my description of this technology) manufactured by Intel using its advanced 22nm manufacturing process featuring 3-D Tri-Gate transistors and co-optimized packaging technology.
This is made possible by a manufacturing access agreement between Tabula, and Intel Custom Foundry, a division of the Technology and Manufacturing Group of Intel Corporation. The 3PLD family will be based on Tabula’s 3D Spacetime architecture and will deliver high-performance, cost-effective solutions for network infrastructure systems requiring high-bandwidth data flows such as Switches, Routers, Packet Inspection appliances, and other high-performance systems. The combination of process and architecture will allow Tabula to produce high-performance programmable circuits that consume significantly less chip area than circuits implemented with traditional FPGA fabrics.
At this week’s Ethernet Technology Summit, Daniel Gitlin, Tabula’s Vice President of Manufacturing Technology, and a veteran in PLD advanced process technology, will discuss Tabula’s approach to overcoming the limitations FPGA technologies have reached in supporting the explosive growth of bandwidth. The Summit will take place at the Doubletree hotel in San Jose, California. Mr. Gitlin will participate in the Ethernet Chipsets session (1-103), an executive panel discussion focusing on the latest advances in Ethernet technology, particularly in 40/100 GbE. The session starts at 3:10pm on Tuesday, February 22nd.
