It has been designed to reduce overall design cycle times and enhance the quality of silicon in complex system-on-chip (SoC) designs, according to Cadence and provides designers with 100% signoff timer accuracy and up to 10X faster turnaround time versus the previous generation solution.
The Conformal Litmus provides customers with:
- The industry’s first signoff static timer integration: With this integration, the Conformal Litmus can accurately model the design and the constraints using the same interpretation as the Tempus Timing Signoff Solution, providing customers with 100% signoff accuracy at the register-transfer level (RTL).
- CDC structural signoff: This verifies structural correctness of CDC in the design from early RTL through implementation flows. Smart analysis and reporting features provide rapid signoff capabilities, potentially saving weeks to months in the design schedule.
- Constraints signoff: Checks for correctness and completeness of constraints at the block level and lets users perform hierarchical block versus top consistency checks at the SoC integration level. The Conformal Litmus smart analysis generates accurate, low-noise reports that shorten debug time and helps users achieve signoff-quality constraints rapidly.
- Multi-CPU parallelisation: Verification can be parallelized across multiple cores, delivering up to 10X faster turnaround time on SoC designs.
“Accelerating SoC delivery to meet tight design schedules while keeping development costs down continues to be a growing customer challenge with today’s complex designs,” said Dr. Chin-Chi Teng, senior vice president and general manager in the Digital & Signoff Group at Cadence. “The new Conformal Litmus provides innovative capabilities that enable our customers to sign off on constraints and CDCs and tape out reliable, high-quality designs on schedule.”
The Conformal Litmus is part of the broader Cadence digital and signoff full flow portfolio which provides better predictability and a faster path to design closure and forms part of Cadence’s Intelligent System Design strategy.
